1. Field of the Invention
The present invention relates to a voltage clamping circuit for a voltage input signal and, more particularly, to a clamping circuit used in an input section of a charge transfer device.
2. Description of the Related Art
Signal input methods for a CTD (Charge Transfer Device) such as a CCD (Charge Coupled Device), BBD (Bucket Brigate Device), or the like include a mean value input bias method, a clamp input bias method, and the like. In the mean value input bias method, it is difficult to effectively utilize a dynamic range of the CTD for a signal, e.g., a video signal, which suffers from a large variation in mean DC level, and the amplitude of an input, signal must be reduced. In the clamp input bias method, an operating point of the CTD is set for a signal having a synchronizing signal component, e.g., a horizontal synchronizing signal of a video signal, so that the dynamic range of the CTD can be effectively utilized. For this reason, in the clamp input bias method, a signal having a larger amplitude than in the mean value input bias method can be input.
FIG. 1 is a block diagram of a conventional clamping circuit used in a CTD which has an input section of the clamp input bias method. A signal from an input signal source 31 is supplied to an input pin 33 of a CTD-IC through a coupling capacitor 32. A signal voltage Va supplied to the input pin 33 is supplied to the inverting input terminal ("-" terminal) of a comparator 34 comprising an operational amplifier, and is also supplied to a CCD 35. On the other hand, the non-inverting input terminal ("+" terminal) of the comparator 34 receives a reference voltage Vb as a clamping voltage from a reference voltage generating circuit 36. The output terminal of the comparator 34 is connected to the drain and gate of an N-channel enhancement-type MOS transistor 37. The source of the MOS transistor 37 is connected to the input pin 33. The MOS transistor 37 serves as a diode.
In this clamping circuit, when the input signal voltage Va applied to the comparator 34 is equal to or higher than the reference voltage Vb, the output from the comparator 34 goes to "0" level, and the MOS transistor 37 is disabled. When the input signal voltage Va is lower than the reference voltage Vb, the output from the comparator 34 goes to "1" level, and the MOS transistor 37 is enabled. Thus, a "1"-level voltage from the comparator 34 is output to the input pin 33. In this case, the input pin 33 is charged by a time constant according to the ON resistance of the transistor 37 and the capacitance of the coupling capacitor 32. When the value Va of the input pin 33 becomes equal to or higher than the reference voltage Vb from the reference voltage generating circuit 36, the output from the comparator 34 is inverted to "0" level. Therefore, a lowest value of the input signal voltage Va is clamped at the reference voltage Vb.
The clamping circuit shown in FIG. 1 clamps the lowest voltage of the input signal voltage Va at the reference voltage Vb. FIG. 2 shows a conventional clamping circuit which clamps a highest voltage of the input signal voltage Va. In this circuit, the gate of the MOS transistor 37 is connected to the input pin 33, so that the highest voltage of the input signal voltage is clamped at the reference voltage Vb.
In the conventional circuit shown in FIG. 1, an upper limit value of the clamping voltage applied to the input pin 33 is equal to a value V.sub.CH =(V.sub.CC -V.sub.th) obtained by subtracting a threshold voltage V.sub.th of the MOS transistor 37 from the "1"-level output voltage (almost equal to a power supply voltage V.sub.CC) from the comparator 34. For this reason, the reference voltage Vb cannot be set at a value equal to or higher than V.sub.CH =(V.sub.CC -V.sub.th). Therefore, when the power supply voltage V.sub.CC is lowered, the value V.sub.CH is decreased, and the setting range of the reference voltage Vb is restricted, thus making circuit design difficult. For example, assume that the reference voltage Vb is required to be set to 4.5 V when the power supply voltage V.sub.CC is set to 5 V. In this case, since the threshold voltage V.sub.th of the N-channel enhancement type MOS transistor 37 is normally about 1 V, V.sub.CC (5 V) - V.sub.th (1 V)&lt;Vb (4.5 V), and the requirement cannot be satisfied. Similarly, in the conventional circuit shown in FIG. 2, when the power supply voltage V.sub.CC is lowered, the value V.sub.CH is decreased, and the setting range of the reference voltage Vb is restricted, thus making circuit design difficult.
In this manner, in the conventional clamping circuit, when the power supply voltage is lowered, the setting range of the reference voltage is restricted, thus making circuit design difficult.